View PAC5253_8389653.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

product data sheet PAC5253 power application controller tm multi-mode power manager tm configurable analog front end tm application specific power drivers tm arm ? cortex tm -m0 controller core www.active-semi.com copyright ? 2016 active-semi, inc.
PAC5253 power application controller table of contents 1. general description ........................................................................................................................................... 7 2. pac family applications .................................................................................................................................... 8 3. product selection summary ............................................................................................................................... 9 4. ordering information .......................................................................................................................................... 9 5. PAC5253 features ........................................................................................................................................... 10 6. absolute maximum ratings .............................................................................................................................. 11 7. architectural block diagram ............................................................................................................................. 12 8. pin configuration .............................................................................................................................................. 13 8.1. PAC5253qa ............................................................................................................................................. 13 9. pin description ................................................................................................................................................. 14 10. multi-mode power manager (mmpm) ............................................................................................................ 19 10.1. features ................................................................................................................................................. 19 10.2. block diagram ........................................................................................................................................ 19 10.3. functional description ............................................................................................................................ 19 10.3.1. multi-mode switching supply (mmss) controller ........................................................................... 19 10.3.2. linear regulators ........................................................................................................................... 21 10.3.3. power up sequence ...................................................................................................................... 22 10.3.4. hibernate mode .............................................................................................................................. 22 10.3.5. power and temperature monitor .................................................................................................... 23 10.3.6. voltage reference .......................................................................................................................... 23 10.4. electrical characteristics ........................................................................................................................ 24 10.5. typical performance characteristics ...................................................................................................... 27 11. configurable analog front end (cafe) .......................................................................................................... 28 11.1. block diagram ........................................................................................................................................ 28 11.2. functional description ............................................................................................................................ 29 11.2.1. differential programmable gain amplifier (da) .............................................................................. 29 11.2.2. single-ended programmable gain amplifier (amp) ....................................................................... 29 11.2.3. general purpose comparator (cmp) ............................................................................................. 29 11.2.4. phase comparator (phc) .............................................................................................................. 29 11.2.5. protection comparator (pcmp) ...................................................................................................... 29 11.2.6. analog output buffer (buf) ............................................................................................................ 30 11.2.7. analog front end i/o (aio) ............................................................................................................ 30 11.2.8. push button (pbtn) ....................................................................................................................... 30 11.2.9. hp dac and lp dac ..................................................................................................................... 30 11.2.10. adc pre-multiplexer ..................................................................................................................... 30 11.2.11. configurable analog signal matrix (casm) .................................................................................. 30 11.2.12. configurable digital signal matrix (cdsm) ................................................................................... 30 11.3. electrical characteristics ........................................................................................................................ 32 11.4. typical performance characteristics ...................................................................................................... 36 12. application specific power drivers (aspd) .................................................................................................... 37 12.1. features ................................................................................................................................................. 37 12.2. block diagram ........................................................................................................................................ 37 12.3. functional description ............................................................................................................................ 37 12.3.1. low-side gate driver ..................................................................................................................... 38 12.3.2. ultra-high-voltage gate driver ....................................................................................................... 38 12.3.3. high-side switching transients ...................................................................................................... 38 12.3.4. power drivers control .................................................................................................................... 39 12.3.5. gate driver fault protection ........................................................................................................... 39 12.4. electrical characteristics ........................................................................................................................ 41 12.5. typical performance characteristics ...................................................................................................... 42 13. adc with auto-sampling sequencer .............................................................................................................. 44 - 2 - rev 1.10? january 28, 2016
PAC5253 power application controller 13.1. block diagram ........................................................................................................................................ 44 13.2. functional description ............................................................................................................................ 44 13.2.1. adc ................................................................................................................................................ 44 13.2.2. auto-sampling sequencer ............................................................................................................. 44 13.2.3. emux control ................................................................................................................................ 45 13.3. electrical characteristics ........................................................................................................................ 45 14. memory system ............................................................................................................................................. 46 14.1. features ................................................................................................................................................. 46 14.2. block diagram ........................................................................................................................................ 46 14.3. functional description ............................................................................................................................ 46 14.3.1. program and data flash ............................................................................................................. 46 14.3.2. sram ............................................................................................................................................. 46 14.4. electrical characteristics ........................................................................................................................ 47 15. clock control system ..................................................................................................................................... 48 15.1. features ................................................................................................................................................. 48 15.2. block diagram ........................................................................................................................................ 48 15.3. functional description ............................................................................................................................ 49 15.3.1. free running clock (frclk) ........................................................................................................ 49 15.3.2. fast clock (fclk) .......................................................................................................................... 49 15.3.3. high-speed clock (hclk) ............................................................................................................. 49 15.3.4. auxiliary clock (aclk) ................................................................................................................... 49 15.3.5. clock gating ................................................................................................................................... 49 15.3.6. ring oscillator (rosc) .................................................................................................................. 49 15.3.7. trimmed 4mhz rc oscillator ......................................................................................................... 49 15.3.8. internal slow rc oscillator ............................................................................................................ 49 15.3.9. crystal oscillator driver ................................................................................................................. 49 15.3.10. external clock input ..................................................................................................................... 49 15.3.11. pll ............................................................................................................................................... 49 15.4. electrical characteristics ........................................................................................................................ 50 16. arm cortex-m0 microcontroller core ............................................................................................................ 51 16.1. features ................................................................................................................................................. 51 16.2. block diagram ........................................................................................................................................ 51 16.3. functional description ............................................................................................................................ 51 16.4. electrical characteristics ........................................................................................................................ 52 16.5. typical performance characteristics ...................................................................................................... 52 17. i/o controller .................................................................................................................................................. 53 17.1. features ................................................................................................................................................. 53 17.2. block diagram ........................................................................................................................................ 53 17.3. functional description ............................................................................................................................ 53 17.4. electrical characteristics ........................................................................................................................ 54 18. serial interface ............................................................................................................................................... 55 18.1. block diagram ........................................................................................................................................ 55 18.2. functional description ............................................................................................................................ 55 18.2.1. i 2 c controller .................................................................................................................................. 55 18.3. uart controller ..................................................................................................................................... 56 18.4. spi controller ......................................................................................................................................... 56 18.5. dynamic characteristics ........................................................................................................................ 57 19. timers ............................................................................................................................................................ 60 19.1. block diagram ........................................................................................................................................ 60 19.2. functional description ............................................................................................................................ 61 19.2.1. timer a ........................................................................................................................................... 61 19.2.2. timer b ........................................................................................................................................... 61 19.2.3. timer c .......................................................................................................................................... 61 19.2.4. timer d .......................................................................................................................................... 62 - 3 - rev 1.10? january 28, 2016
PAC5253 power application controller 19.2.5. watchdog timer ............................................................................................................................. 62 19.2.6. soc bus watchdog timer ............................................................................................................. 62 19.2.7. wake-up timer .............................................................................................................................. 62 19.2.8. real-time clock ............................................................................................................................. 62 20. thermal characteristics ................................................................................................................................. 63 21. application examples ..................................................................................................................................... 64 22. package outline and dimensions .................................................................................................................. 66 22.1. tqfn88-43 package outline and dimensions ...................................................................................... 66 23. change list .................................................................................................................................................... 67 24. legal information ........................................................................................................................................... 68 - 4 - rev 1.10? january 28, 2016
PAC5253 power application controller list of tables table 1. product selection summary ..................................................................................................................... 9 table 2. ordering information ................................................................................................................................. 9 table 3. absolute maximum ratings .................................................................................................................... 11 table 4. multi-mode power manager and system pin description ....................................................................... 14 table 5. configurable analog front end pin description ...................................................................................... 15 table 6. application specific power drivers pin description ................................................................................ 16 table 7. i/o ports pin description ........................................................................................................................ 17 table 8. multi-mode switching supply controller electrical characteristics ......................................................... 24 table 9. linear regulators electrical characteristics ........................................................................................... 26 table 10. power system electrical characteristics .............................................................................................. 26 table 11. differential programmable gain amplifier (da) electrical characteristics ............................................. 32 table 12. single-ended programmable gain amplifier (amp) electrical characteristics ..................................... 32 table 13. general purpose comparator (cmp) electrical characteristics ........................................................... 33 table 14. phase comparator (phc) electrical characteristics ............................................................................. 33 table 15. protection comparator (pcmp) electrical characteristics .................................................................... 33 table 16. analog output buffer (buf) electrical characteristics .......................................................................... 33 table 17. analog front end i/o (aio) electrical characteristics ........................................................................... 35 table 18. push button (pbtn) electrical characteristics ..................................................................................... 35 table 19. hp dac and lp dac electrical characteristics ................................................................................... 35 table 20. power driver resources by part number ............................................................................................. 38 table 21. microcontroller port and pwm to power driver mapping ...................................................................... 39 table 22. power driver delay configuration ......................................................................................................... 39 table 23. gate drivers electrical characteristics ................................................................................................. 41 table 24. open-drain drivers electrical characteristics ....................................................................................... 41 table 25. adc and auto-sampling sequencer electrical characteristics ............................................................. 45 table 26. memory system electrical characteristics ............................................................................................ 47 table 27. clock control system electrical characteristics ................................................................................... 50 table 28. microcontroller and clock control system electrical characteristics .................................................... 52 table 29. i/o controller electrical characteristics ................................................................................................ 54 table 30. serial interface dynamic characteristics .............................................................................................. 57 table 31. i 2c dynamic characteristics ................................................................................................................. 58 table 32. thermal characteristics ........................................................................................................................ 63 - 5 - rev 1.10? january 28, 2016
PAC5253 power application controller list of figures figure 1-1. power application controller ................................................................................................................ 7 figure 2-1. simplified application diagram ............................................................................................................ 8 figure 7-1. architectural block diagram ............................................................................................................... 12 figure 8-1. PAC5253qa pin configuration (tqfn88-43 package) ..................................................................... 13 figure 9-1. power supply bypass capacitor routing .......................................................................................... 18 figure 10-1. multi-mode power manager ............................................................................................................. 19 figure 10-2. buck mode ....................................................................................................................................... 20 figure 10-3. ultra-high-voltage buck mode ......................................................................................................... 20 figure 10-4. ac/dc flyback mode ....................................................................................................................... 21 figure 10-5. linear regulators ............................................................................................................................. 22 figure 10-6. power up sequence ........................................................................................................................ 22 figure 11-1. configurable analog front end ........................................................................................................ 28 figure 12-1. application specific power drivers ................................................................................................... 37 figure 12-2. typical gate driver connections ...................................................................................................... 38 figure 12-3. high-side switching transients and optional circuitry .................................................................... 39 figure 13-1. adc with auto-sampling sequencer ................................................................................................ 44 figure 14-1. memory system ............................................................................................................................... 46 figure 15-1. clock control system ...................................................................................................................... 48 figure 16-1. arm cortex-m0 microcontroller core .............................................................................................. 51 figure 17-1. i/o controller .................................................................................................................................... 53 figure 18-1. serial interface ................................................................................................................................. 55 figure 18-2 . i2c timing diagram .......................................................................................................................... 59 figure 19-1. timers a, b, c, and d ...................................................................................................................... 60 figure 19-2. soc bus watchdog and wake-up timer ........................................................................................ 61 figure 19-3. real-time clock and watchdog timer ............................................................................................. 61 figure 21-1. 3-phase motor using PAC5253 (simplified diagram) ...................................................................... 64 figure 21-2. solar micro-inverter using PAC5253 (simplified diagram) .............................................................. 64 figure 21-3. motor with led lighting using PAC5253 (simplified diagram) ....................................................... 65 - 6 - rev 1.10? january 28, 2016
PAC5253 power application controller 1. general description the PAC5253 belongs to active-semi's broad portfolio of full-featured power application controller tm (pac) products that are highly optimized for controlling and powering next generation smart energy appliances, devices, and equipment. these application controllers integrate a 50mhz arm ? cortex tm -m0 32-bit microcontroller core with active-semi's proprietary and patent-pending multi-mode power manager tm , config urable analog front end tm , and application specific power drivers tm to form the most compact microcontroller-based power and general purpose application systems ranging from digital power supply to motor control. the pac52xx microcontroller features up to 32kb of embedded flash and 8kb of sram memory, a high-speed 10-bit 1 s analog-to-digital converter ( adc) with dual auto-sampling sequencers, 5v/3.3v i/os, flexible clock sources, timers, a versatile 14-channel pwm engine, and several serial interfaces. the multi-mode power manager (mmpm) provides all-in-one efficient power management solution for multiple types of power sources. it features a configurable multi-mode switching supply controller capable of operating in buck, flyback, or boost mode, and up to four linear regulated voltage supplies. the application specific power drivers (aspd) are high- voltage and ultra-high-voltage power drivers designed for each target set of control applications, including half bridge, h- bridge, 3-phase, intelligent power module (ipm), and general purpose driving. the configurable analog front end (cafe) comprises differential programmable gain amplifiers, single-ended programmable gain amplifiers, comparators, digital-to- analog converters, and i/os for programmable and inter-connectible signal sampling, feedback amplification, and sensor monitoring of multiple analog input signals. together, these modules and microcontroller enable a wide range of compact applications with highly integrated power management, driving, feedback, and control for dc supply up to 52v and for line ac supply. the PAC5253 is available in a 43-pin 8x8 tqfn package. the pac family includes a range of part numbers optimized to work with different targeted primary applications. - 7 - rev 1.10? january 28, 2016 figure 1-1 . power application controller 50mhz arm cortex-m0 microcontroller core & memory 1-cycle 32-bit multiplier, 24-bit rtc, 24-bit wdt, 24-bit systick, nvic, flash & sram 50mhz arm cortex-m0 microcontroller core & memory 1-cycle 32-bit multiplier, 24-bit rtc, 24-bit wdt, 24-bit systick, nvic, flash & sram data acquisition & sequencer 10-bit 1 s adc, dual auto-sampling sequencer data acquisition & sequencer 10-bit 1 s adc, dual auto-sampling sequencer pwm engine 16-bit timers, hw dead-time control, 10ns resolution control pwm engine 16-bit timers, hw dead-time control, 10ns resolution control serial interface spi, i 2 c, uart serial interface spi, i 2 c, uart application specific power drivers ultra-high voltage high- side gate drivers, low-side gate drivers, mv open-drain drivers application specific power drivers ultra-high voltage high- side gate drivers, low-side gate drivers, mv open-drain drivers multi-mode power manager ac/dc, dc/dc, linear regulators multi-mode power manager ac/dc, dc/dc, linear regulators configurable analog front end 3 differential pgas, 4 single-ended pgas, 10 comparators, 2 dacs (10-bit & 8-bit), temperature monitor configurable analog front end 3 differential pgas, 4 single-ended pgas, 10 comparators, 2 dacs (10-bit & 8-bit), temperature monitor
PAC5253 power application controller 2. pac family applications general purpose high-voltage system controllers home appliances power tools motor controllers led lighting controllers uninterruptible power supply (ups) solar micro-inverters wireless power controllers digital power controllers industrial applications - 8 - rev 1.10? january 28, 2016 figure 2-1 . simplified application diagram 50mhz arm cortex-m0 microcontroller core & memory data acquisition & sequencer pwm engine serial interface application specific power drivers multi-mode power manager configurable analog front end m buck/ boost/ flyback c spi/i2c/uart monitoring signals pac52xx
PAC5253 power application controller 3. product selection summary table 1 . product selection summary part number pin pkg power manager configurable analog front end application specific power drivers microcontroller primary applicatio n i n p u t v o l t a g e m u l t i - m o d e s w d i f f - p g a p g a c o m p a r a t o r d a c a d c c h a n n e l p o w e r d r i v e r p w m c h a n n e l f a u l t p r o t e c t s p e e d ( m h z ) f l a s h ( k b ) s r a m ( k b ) g p i o i n t e r f a c e x t a l PAC5253 43-pin 8x8 tqfn 5.2- 52v y 3 4 10 2 9 4 ls (1a/1a) 3 hs (0.25a/0.5a) 7 int + ext 50 32 8 25 spi i 2 c uart swd y uhv 3 half bridge, 3-phase control notes: diff-pga = differential programmable gain amplifier, gd = gate driver, hs = high-side , ls = low-side, od = open-drain driver, pga = programmable gain amplifier, uhv = ultra-high-voltage. 4. ordering information table 2 . ordering information part number (1) temperature range package pins packing PAC5253qa -40c to 105c tqfn88-43 43 + exposed pad tray (1) see product selection summary for product features for each part number. - 9 - rev 1.10? january 28, 2016
PAC5253 power application controller 5. PAC5253 features proprietary multi-mode power manager multi-mode switching supply controller configurable as high-voltage or ultra-high-voltage buck, ac/dc or flyback dc supply up to 52v or line ac input 4 linear regulators with power and hibernate management power and temperature monitor, warning, and fault detection proprietary configurable analog front end 10 analog front end i/o pins 3 differential programmable gain amplifiers 4 single-ended programmable gain amplifiers 10 comparators 2 dacs (10-bit and 8-bit) proprietary application specific power drivers 4 low-side and 3 600v high-side gate drivers 1a/1a low-side, 0.25a/0.5a high-side, gate driving capability configurable delays and fast fault protection 50mhz arm cortex-m0 32-bit microcontroller core fast single cycle 32-bit x 32-bit multiplier 24-bit systick timer nested vectored interrupt controller (nvic) with 20 external interrupts wake-up interrupt controller allowing power-saving sleep modes clock-gating allowing low power operation 32kb flash and 8kb sram memory 10-bit 1 s adc with multi-input/multi-sample control engine 9 adc inputs including input from configurable analog front end 3.3v i/os 2 general purpose i/os with tri-state, and dedicated analog input to adc true 5v i/os 13 general purpose i/os with tri-state, pull-up and pull-down and dedicated i/o supply configurable between true 5v and 3.3v i/os flexible clock and pll from internal 2% oscillator, ring oscillator, external clock, or crystal 9 timing generators four 16-bit timers with up to 16 pwm/cc blocks and 7 independent dead-time controllers 24-bit watchdog timer 4s or 8s watchdog timer 24-bit real time clock 24-bit systick timer wake-up timer for sleep modes from 0.125s to 8s spi, i 2 c, and uart communication interfaces swd debug interface with interface disable function - 10 - rev 1.10? january 28, 2016
PAC5253 power application controller 6. absolute maximum ratings table 3 . absolute maximum ratings (do not exceed these limits to prevent damage to the device. exposure to absolute maximum rating conditions for long periods may affect device reliability.) parameter value unit vhm, drm to vss -0.3 to 54 v vp to vss -0.3 to 17 v csm, rego to vss -0.3 to v p + 0.3 v vsys, aio6/.. to vss -0.3 to 6 v vcc33 to vss -0.3 to 4.1 v vcc18 to vss -0.3 to 2.5 v aiox/.. (except aio6/..), vccio to vss -0.3 to v sys + 0.3 v pdx/.., pex/.. to vss -0.3 to v ccio + 0.3 v pcx/.. to vss -0.3 to v cc33 + 0.3 v drlx to vss -0.3 to v p + 0.3 v dxbx to vss -0.3 to 630 v dxsx to vss -11 to 610 v dxsx allowable offset slew rate (dv dxsx /dt) -50 to 50 v/ns dxbx, dxhx to respective dxsx -0.3 to 22 v vss, vsys, drm, drlx, dxhx, rego rms current (1) 0.2 a rms vp rms current (1) 0.6 a rms operating temperature range -40 to 105 c electrostatic discharge (esd) human body model (jedec) 2 kv charge device model (jedec) 800 v machine model (jedec) 200 v (1) peak current can be 10 times higher than rms value for pulses shorter than 10 s. - 11 - rev 1.10? january 28, 2016
PAC5253 power application controller 7. architectural block diagram - 12 - rev 1.10? january 28, 2016 figure 7-1 . architectural block diagram 8kb/4kb sram 32kb/16kb flash gpio (10) spi watchdog rtc system control debug 10-bit adc dac (2) clock control auto sampling multi- mode switching supply linear regu- lators (4) daxp/pcmpx daxn ampx/cmpx/phcx pga/ cmp (4) aio control (10) aiox hsgd (3) drlx dxhx dxsx dxbx lsgd (4) application specific power drivers configurable analog front end multi-mode power manager rego vccio vcc18 diff-pga/ pcmp (3) vhm drm csm vp vcc33 vsys vss buf6 pbtn data acquisition & sequencer pcx, pdx, pex i 2 c uart spicsx, spimiso, spimosi, spiclk i2csda, i2cscl uartrx, uarttx nreset1 pwmax, pwmbx pwm / cc (14) pwm engine dead time (7) timers (4) bridge swdio, swdcl PAC5253 power application controller adx arm cortex-m0 core m u x a h b / a p b p a c s o c b u s
PAC5253 power application controller 8. pin configuration 8.1. PAC5253qa - 13 - rev 1.10? january 28, 2016 figure 8-1 . PAC5253qa pin configuration (tqfn88-43 package) 1 2 vcc18 3 4 pc2/ad2 5 vcc33 6 7 vss 8 aio0/da0n 9 aio1/da0p/pcmp0 10 aio2/da1n 11 aio3/da1p/pcmp1 12 aio4/da2n 13 aio5/da2p/pcmp2 14 aio6/amp6/cmp6/buf6/pbtn 1 5 r e g o 4 3 4 2 v c c i o 4 1 p e 5 / s p i c s 2 / i 2 c s d a 4 0 p e 4 / s p i c s 1 / i 2 c s c l 3 9 p e 3 / s p i c s 0 / n r e s e t 1 3 8 p e 2 / s p i m i s o / u a r t r x 3 7 p e 1 / s p i m o s i / u a r t t x 3 6 p e 0 / s p i c l k 3 5 p d 0 / s w d i o 3 4 p d 1 / s w d c l / e x t c l k 27 dxb0 26 dxh0 25 dxs0 aio7/amp7/cmp7/phc7 aio8/amp8/cmp8/phc8 aio9/amp9/cmp9/phc9 1 6 c s m 1 7 v p 1 8 v h m 1 9 d r m 2 0 2 1 d r l 0 2 2 d r l 1 2 3 d r l 2 2 4 d r l 3 28 dxs1 30 dxb1 29 dxh1 33 dxb2 32 dxh2 31 dxs2 PAC5253qa tqfn88-43 ep (vss) p d 2 / p w m a 7 / p w m b 1 v s y s
PAC5253 power application controller 9. pin description table 4 . multi-mode power manager and system pin description pin name pin number type description csm 17 analog switching supply current sense input. connect to the positive side of the current sense resistor. drm 20 analog switching supply driver output. connect to the base or gate of the external power npn or n-channel mosfet. see pac user guide and application notes. ep (vss) ep power exposed pad. mu st be connected to v ss in a star ground configuration. connect to a large pcb copper area for power dissipation heat sinking. rego 16 power system regulator output. connect to v sys directly or through an external power-dissipating resistor. vcc18 1 power internally generated 1.8v core power supply. connect a 2.2f or higher value ceramic capacitor from v cc18 to v ssa . see figure 9-1. power supply bypass capacitor routing below. vcc33 4 power internally generated 3.3v power supply. connect a 2.2f or higher value ceramic capacitor from v cc33 to v ssa . see pcb layout note below. vccio 43 power internally generated digital i/o power supply. connect a 4.7f or higher value ceramic capacitor from v ccio to v ssa . see figure 9-1. power supply bypass capacitor routing below. vhm 19 power switching suppl y controller supply input. connect a 1f or higher value ceramic capacitor, or a 0.1f ceramic capacitor in parallel with a 10f or higher electrolytic capacitor from v hm to v ssp . this pin requires good capacitive bypassing to v ssp , so the ceramic capacitor must be connected with a shorter than 10mm trace from the pin. see figure 9-1. power supply bypass capacitor routing below. vp 18 power main po wer supply. provides power to the power drivers as well as voltage feedback path for the switching supply. connect a properly sized supply bypass capacitor in parallel with a 0.1f ceramic capacitor from v p pin to v ss for voltage loop stabilization. this pin requires good capacitive bypassing to v ss , so the ceramic capacitor must be connected with a shorter than 10mm trace from the pin. see see figure 9-1. power supply bypass capacitor routing below. vss 2 power ground. vsys 15 power 5v system power supply. connect a 4.7f or higher value ceramic capacitor from v sys to v ssp . see figure 9-1. power supply bypass capacitor routing below. - 14 - rev 1.10? january 28, 2016
PAC5253 power application controller table 5 . configurable analog front end pin description pin name pin number function type description aio0/da0n 5 aio0 i/o analog front end i/o 0. da0n analog differential pga 0 negative input. aio1/da0p/pcmp0 6 aio1 i/o analog front end i/o 1. da0p analog differential pga 0 positive input. pcmp0 analog protection comparator input 0. aio2/da1n 7 aio2 i/o analog front end i/o 2. da1n analog differential pga 1 negative input. aio3/da1p/pcmp1 8 aio3 i/o analog front end i/o 3. da1p analog differential pga 1 positive input. pcmp1 analog protection comparator input 1. aio4/da2n 9 aio4 i/o analog front end i/o 4. da2n analog differential pga 2 negative input. aio5/da2p/pcmp2 10 aio5 i/o analog front end i/o 5. da2p analog differential pga 2 positive input. pcmp2 analog protection comparator input 2. aio6/amp6/cmp6/buf6/pbtn 11 aio6 i/o analog front end i/o 6. amp6 analog pga input 6. cmp6 analog comparator input 6. buf6 analog buffer output 6. pbtn analog push button input. aio7amp7/cmp7/phc7 12 aio7 i/o analog front end i/o 7. amp7 analog pga input 7. cmp7 analog comparator input 7. phc7 analog phase comparator input 7. aio8/amp8/cmp8/phc8 13 aio8 i/o analog front end i/o 8. amp8 analog pga input 8. cmp8 analog comparator input 8. phc8 analog phase comparator input 8. aio9/amp9/cmp9/phc9 14 aio9 i/o analog front end i/o 9. amp9 analog pga input 9. cmp9 analog comparator input 9. phc9 analog phase comparator input 9. - 15 - rev 1.10? january 28, 2016
PAC5253 power application controller table 6 . application specific power drivers pin description pin name pin number type description drl0 21 analog low-side gate driver 0. drl1 22 analog low-side gate driver 1. drl2 23 analog low-side gate driver 2. drl3 24 analog low-side gate driver 3. dxb0 27 analog ultra-high-voltage high-side gate driver bootstrap 0. dxb1 30 analog ultra-high-voltage high-side gate driver bootstrap 1. dxb2 33 analog ultra-high-voltage high-side gate driver bootstrap 2. dxh0 26 analog ultra-high-voltage high-side gate driver 0. dxh1 29 analog ultra-high-voltage high-side gate driver 1. dxh2 32 analog ultra-high-voltage high-side gate driver 2. dxs0 25 analog ultra-high-voltage high-side gate driver source 0. dxs1 28 analog ultra-high-voltage high-side gate driver source 1. dxs2 31 analog ultra-high-voltage high-side gate driver source 2. - 16 - rev 1.10? january 28, 2016
PAC5253 power application controller table 7 . i/o ports pin description pin name pin number function type description pc2/ad2 3 pc2 i/o i/o port c2. ad2 analog adc input 2. pd0/swdio 36 pd0 i/o i/o port d0. swdio i/o serial wire debug i/o. pd1/swdcl/extclk 35 pd1 i/o i/o port d1. swdcl i serial wire debug clock. extclk i external clock. pd2/pwma3/pwma4/pwmb0 34 pd2 i/o i/o port d2. pwma3 i/o timer a pwm/capture 3. pwma4 i/o timer a pwm/capture 4. pwmb0 i/o timer b pwm/capture 0. pe0/spiclk 37 pe0 i/o i/o port e0. spiclk i/o spi clock. pe1/spimosi/uarttx 38 pe1 i/o i/o port e1. spimosi i/o spi master out slave in (mosi). uarttx o uart transmit output. pe2/spimiso/uartrx 39 pe2 i/o i/o port e2. spimiso i/o spi master in slave out (miso). uartrx i uart receive input. pe3/spics0/nreset1 40 pe3 i/o i/o port e3. spics0 o spi chip select 0. nreset1 i reset input 1 (active low). pe4/spics1/i2cscl 41 pe4 i/o i/o port e4. spics1 o spi chip select 1. i2cscl i/o i2c clock. pe5/spics2/i2csda 42 pe5 i/o i/o port e5. spics2 o spi chip select 2. i2csda i/o i2c data. - 17 - rev 1.10? january 28, 2016
PAC5253 power application controller - 18 - rev 1.10? january 28, 2016 figure 9-1 . power supply bypass capacitor routing
PAC5253 power application controller 10. multi-mode power manager (mmpm) 10.1. features multi-mode switching supply controller configurable as high voltage or ultra-high-voltage buck, flyback ac/dc dc supply up to 52v or line ac input 4 linear regulators with power and hibernate management power and temperature monitor, warning, and fault detection 10.2. block diagram 10.3. functional description the multi-mode power manager ( figure 10-1 ) is optimized to efficiently provide "all-in-one" power management required by the pac and associated application circuitry from a wide range of input power sources. it incorporates a dedicated multi- mode switching supply (mmss) controller operable as a buck, flyback, or boost converter to efficiently convert power from a dc or ac input source to generate a main supply output v p . four linear regulators provide v sys , v ccio , v cc33 , and v cc18 supplies for 5v system, 5v or 3.3v i/o, 3.3v mixed signal, and 1.8v microcontroller core circuitry. the power manager also handles system functions including internal reference generation, timers, hibernate mode management, and power and temperature monitoring. 10.3.1. multi-mode switching supply (mmss) controller the mmss controller drives an external power transistor for pulse-width modulation switching of an inductor or transformer for power conversion. the drm output drives the gate of the n-channel mosfet or the base of the npn between the v hm on state and v ss off state at proper duty cycle and switching frequency to ensure that the main supply voltage v p is regulated. the v p regulation voltage is initially set to 15v during start up, and can be reconfigured to be 5v, - 19 - rev 1.10? january 28, 2016 figure 10-1 . multi-mode power manager imod dac csm curr sense drm driver multi-mode power manager vhm vssp pwm logic error amp linear reg vccio linear reg vcc33 linear reg vcc18 system supply reg voltage setting vp rego vsys comp & curr limit clamp error comp multi-mode switching supply controller power ok & ovp m u x m u x start up & mode ctrl 1.2v hibernate 2.5v v ref timers power & temp mon vss m u x v mon v thref v temp
PAC5253 power application controller 9v, or 12v by the microcontroller after initialization. 1 when v p is lower than the target regulation voltage, the internal feedback control circuitry causes the inductor current to increase to raise v p . conversely, when v p is higher than the regulation voltage, the feedback loop control causes the inductor current to decrease to lower v p . the feedback loop is internally stabilized. the output current capability of the switching supply is determined by the external current sense resistor. in the high-side current sense buck mode, the inductor current signal is sensed differentially between the csm pin and v p , and has a peak current limit threshold of 0.26v. in the low-side current sense flyback or boost mode, the inductor current signal is sensed differentially between the csm pin and v ss , and has a peak current limit threshold of 1v. the mmss controller is flexible and configurable as a buck, flyback, or boost converter. input sources include battery supply for buck mode ( figure 10-2 ), and ac line supply voltage range for ultra-high-voltage buck mode ( figure 10-3 ), ac/dc flyback mode ( figure 10-4 ). the mmss controller operational mode is determined by external configuration and register setting from the microcontroller after power up. it can operate in either high-side or low-side current sense mode, and does not require external feedback loop compensation circuitry. for optional extended application range, the mmss also incorporates additional digital control by the microcontroller to add accurate computations for outer feedback loop control such as power factor correction and accurate current control. 1 note that on any device with ultra-high voltage drivers (pac525x), it is invalid to set vp to less than 12v. - 20 - rev 1.10? january 28, 2016 figure 10-2 . buck mode vhm drm csm vp pac52xx v p (15v default) v in vhm drm csm vp PAC5253 v in figure 10-3 . ultra-high-voltage buck mode vhm drm csm vp pac5210 v p (15v default) v ac (120v/230v) vhm drm csm vp PAC5253 v ac (120v/230v)
PAC5253 power application controller the mmss detects and selects between high-side and low-side mode during start up based on the placement of the current sense resistor and the csm pin voltage. it employs a safe start up mode with 9.5khz switching frequency until v p exceeds 4.3v under-voltage-lockout threshold, then transitions to the 45khz default switching frequency for at least 6ms to bring v p close to the target voltage, before enabling the linear regulators. any extra load should only be applied after the supplies are available and the microprocessor has initialized. the switching frequency can be reconfigured by the microprocessor to be 181khz to 500khz in the high switching frequency mode for battery-based applications, and to be 45khz to 125khz in the low switching frequency mode for ac applications. upon initialization, the microcontroller must reconfigure the mmss to the desired settings for v p regulation voltage, switching mode, switching frequency, and v hm clamp. refer to the pac application notes and user guide for mmss controller design and programming. if a stable external 5v to 15v power source is available, it can power the v p main supply and all the linear regulators directly without requiring the mmss controller to operate. in such applications, v hm can be connected directly to v p and the microcontroller should disable the mmss upon initialization to reduce power loss. 10.3.2. linear regulators the mmpm includes up to four linear regulators. the system supply regulator is a medium voltage regulator that takes the v p supply and sources up to 200ma at rego until v sys , externally coupled to rego, reaches 5v. this allows a properly rated external resistor to be connected from rego to v sys to close the current loop and offload power dissipation between v p and v sys . once v sys is abo ve 4v, the three additional 40ma linear regulators for v ccio , v cc33 , and v cc18 supplies sequentially power up. figure 10-5 shows typical circuit connections for the linear regulators. for 5v i/o systems, short the v ccio pin to v sys to bypass the v ccio regulator. for 3.3v i/o systems, the v ccio regulator generates 3.3v. the v cc33 and v cc18 regulators generate 3.3v and 1.8v, respectively. when v sys , v ccio , v cc33 , and v cc18 are all above their respective power good threshold, and the configurable power on reset duration has expired, the microcontroller is initialized. - 21 - rev 1.10? january 28, 2016 figure 10-4 . ac/dc flyback mode PAC5253 vhm drm csm vp v p (15v default) v ac (120v/230v)
PAC5253 power application controller 10.3.3. power up sequence the mmpm follows a typical power up sequence as in the figure 10-6 below. a typical sequence begins with input power supply being applied, followed by the safe start up and start up durations to bring the switching supply output v p to 15v, before the linear regulators are enabled. when all the supplies are ready, the internal clocks become available, and the microcontroller starts executing from the program memory. during initialization, the microcontroller can reconfigure the switching supply to a different v p regulation voltage such as 15v and to an appropriate switching frequency and switching mode. the total loading on the switching supply must be kept below 25% of the maximum output current until after the reconfiguration of the switching supply is complete. for ac input supply applications, the start up sequence includes an additional charging time for v hm depending on the start-up resistor and capacitor values. 10.3.4. hibernate mode the ic can go into an ultra-low power hibernate mode via the microcontroller firmware or via the optional push button (pbtn, see push button description in configurable analog front end ). in hibernate mode, only a minimal amount (typically 18 a) of current is used by v hm , and the mmss controller and all internal regulators are shut down to eliminate power drain from the output supplies. the system exits hibernate mode after a wake-up timer duration (configurable from 125ms to 8s or infinite) has expired or, if push button enabled, after an additional push button event has been detected. - 22 - rev 1.10? january 28, 2016 figure 10-5 . linear regulators vp rego PAC5253 v sys & v ccio (5v) v p (12v typical) vsys vccio vcc33 vcc18 vss vssa (1) 4.7 f 1 f 1 f 5v i/o connection shown. connect instead to a 4.7 f capacitor for 3.3v i/o. (1) figure 10-6 . power up sequence v sys and v ccio (5v) v p (5v/9v/12v/15v) v cc33 (3.3v) v cc18 (1.8v) safe start up v in or v hm 14.8v 4.3v start up 4v 76% microcontroller initializing power-on- reset delay 6ms soc.pwrcfg.treset + 10.5 ms (default: 1ms + 10.5ms = 11.5ms) microcontroller reset v sys and v ccio v p v cc33 v cc18 internal clocks v in or v hm power on reset regulators enabled v p (start up default) reconfiguration by firmware system operation microcontroller executing
PAC5253 power application controller when exiting the hibernate mode, the power manager goes through the start up cycle and the microcontroller is reinitialized. only the persistent power manager status bits (resets a nd faults) are retained during hibernation. 10.3.5. power and temperature monitor w henever any of the v sys , v ccio , v cc33 , or v cc18 power supplies falls belo w their respective power good threshold voltage, a fault event is detected and the microcontroller is reset. the microcontroller stays in the reset state until v sys , v ccio , v cc33 , and v cc18 supply rails are all good again and the reset time has expired . a microcontroller reset can also be initiated by a maskable temperature fault event that occurs when the ic temperature reaches 170 c. the fault status bits are persistent during reset, and can be read by the microcontroller upon re-initialization to determine the cause of previous reset. a power monitoring signal v mon is provided onto the adc pre-multiplexer for monitoring various internal power supplies. v mon can be set to be v cc18 , 0.4 ? v cc33 , 0.4 ? v ccio , 0.4 ? v sys , 0.1 ? v rego , 0.1 ? v p , 0.0333 ? v hm , or the internal compensation voltage v comp for switching supply power monitoring. for power and temperature warning, a v p low event at 77% of the regulation voltage and an ic temperature warning event at 140 c are provided as maskable interrupts to the microcontroller. t hese warnings allow the microcontroller to safely power down the system. in addition to the temperature warning interrupt and fault reset, a temperature monitor signal v temp = 1.5 + 5.04e-3 ? (t - 25 c ) (v) is provided onto the adc pre-multiplexer for ic temperature measurement. 10.3.6. voltage reference the reference block includes a 2.5v high precision reference voltage that provides the 2.5v reference voltage for the adc, the dacs, and the 4-level programmable threshold voltage v thref (0.1v, 0.2v, 0.5v, and 1.25v). - 23 - rev 1.10? january 28, 2016
PAC5253 power application controller 10.4. electrical characteristics table 8 . multi-mode switching supply controller electrical characteristics (v hm = 24v, v p = 12v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max unit input supply (v hm ) i hib;vhm v hm hibernate mode supply current v hm , hibernate mode 18 36 a i su;vhm v hm start up supply current v hm < v uvlor;vhm 75 120 a i op;vhm v hm operating supply current drm floating 0.3 0.5 ma v op:vhm v hm operating voltage range 5.2 52 v v uvlor;vhm v hm under-voltage lockout rising 13.5 14.5 16 v v uvlof;vhm v hm under-voltage lockout falling 6.8 7.5 8.1 v v clamp;vhm v hm clamp voltage clamp enabled, sink current = 100 a 23 26.6 v i clamp;vhm v hm clamp sink current limit clamp enabled 0.72 1.2 ma output supply and feedback (v p ) v reg;vp v p output regulation voltage programmable to 5v, 9v, 12v, or 15v load = 0 to 500ma -7 -1 5 % k pok;vp v p power ok threshold v p rising, hysteresis = 10% 82 87 92 % k ovp;vp v p over voltage protection threshold v p rising, hysteresis = 15% mmpm controller enabled 136 % switching control f swmacc;drm switching frequency accuracy -10 10 % f swm;drm switching frequency programmable range high frequency mode, 8 settings 181 500 low frequency mode, 8 settings 45 125 khz f ssu;drm safe start up switching frequency 9.5 khz t onmin;drm minimum on time 440 ns t offmin;drm minimum off time low duty-cycle & low-frequency mode low duty-cycle & high-frequency mode high duty-cycle mode 25 440 820 % ns ns - 24 - rev 1.10? january 28, 2016
PAC5253 power application controller symbol parameter conditions min typ max unit current sense (csm pin) v det;csm csm mode detection threshold rising, hysteresis = 50mv 0.40 0.55 0.69 v v hslim;csm high-side current limit threshold 181khz, duty = 25%, relative to vp 0.17 0.26 0.35 v v lslim;csm low-side current limit threshold 45khz, duty = 25% 0.7 1 1.48 v t blank;csm current sense blanking time 200 ns v prot;csm low-side abnormal current sense protection threshold v p < 4.3v 0.8 v p > 4.3v 1.9 v gate driver output (drm pin) v oh;drm high-level output voltage i drm = -20ma v hm ? 1.4 v v ol;drm low-level output voltage i drm = 20ma 0.6 v i oh;drm high-level output source current v drm = v hm - 5v -0.1 a i ol;drm low-level output sink current v drm = 5v 0.25 a t pd;drm strong pull down pulse width high-side current sense mode 240 ns - 25 - rev 1.10? january 28, 2016
PAC5253 power application controller table 9 . linear regulators electrical characteristics (v p = 12v and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t v op;vp v p operating voltage range 4.5 16 v v uvlo;vp v p under-voltage-lockout threshold v p rising, hysteresis = 0.2v 4 4.3 4.5 v i q;vp v p quiescent supply current power manager only, including i q;vsys 400 750 a i q;vsys v sys quiescent supply current v ccio , v cc33 , and v cc18 regulators only 350 600 a v sys v sys output voltage load = 10 a to 200ma 4.8 5 5.18 v v ccio v ccio output voltage load = 10ma v ccio shorted to v sys v sys v v ccio from regulator 3.152 3.3 3.398 v cc33 v cc33 output voltage load = 10ma 3.185 3.3 3.415 v v cc18 v cc18 output voltage load = 10ma 1.834 1.9 1.979 v i lim;vsys v sys regulator current limit 220 330 ma i lim;vccio v ccio regulator current limit 45 80 ma i lim;vcc33 v cc33 regulator current limit 45 80 ma i lim;vcc18 v cc18 regulator current limit 45 80 ma k scfb short circuit current fold back 50 % v do;vsys v sys dropout voltage v p =5v, i sys =100ma 350 680 mv v uvlo;vsys v sys under-voltage-lockout threshold v sys rising, hysteresis = 0.2v 3.5 4 4.4 v k pokio v ccio power ok threshold v ccio rising, hysteresis = 10% 75 82 89 % k pok33 v cc33 power ok threshold v cc33 rising, hysteresis = 10% 71 78 85 % k pok18 v cc18 power ok threshold v cc18 falling, hysteresis = 10% 58 66 74 % table 10 . power system electrical characteristics (v sys = v ccio = 5v, v cc33 = 3.3v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t v ref reference voltage t a = 25c 2.487 2.5 2.513 v t a = - 40c to 105c 2.463 2.5 2.537 k mon power monitoring voltage (v mon ) coefficient v cc18 1 v/v v sys , v ccio , v cc33 0.4 v p , v rego 0.1 v hm 0.0333 v temp temperature monitor voltage at 25c t a = 25c, at adc 1.475 1.5 1.540 v k temp temperature monitor coefficient at adc 5.04 mv/k t warn over-temperature warning threshold hysteresis = 10 c 140 c t fault over-temperature fault threshold hysteresis = 10 c 170 c - 26 - rev 1.10? january 28, 2016
PAC5253 power application controller 10.5. typical performance characteristics (v p = 12v and t a = 2 5 c unless otherwise specified.) - 27 - rev 1.10? january 28, 2016 0 0.1 0.2 0.3 0.4 0.5 100 90 80 70 60 50 40 30 20 10 0 p a c m m p m - 0 0 1 e f f i c i e n c y ( % ) buck mode efficiency vs. output current v in = 48v v in = 24v output current (a) v p = 12v, f sw;drm = 181khz 0 0.5 1 1.5 2 2.5 100 90 80 70 60 50 40 30 20 10 0 p a c m m p m - 0 0 3 e f f i c i e n c y ( % ) ac/dc flyback mode efficiency vs. output current v ac = 230v v ac = 120v output current (a) v p = 12v, f sw;drm = 45khz -40 0 40 80 120 80 70 60 50 40 30 20 10 0 p a c m m p m - 0 0 5 o n r e s i s t a n c e ( ) drm driver output on resistance vs. temperature temperature ( c) pull up pull down 20 30 40 50 60 50 40 30 20 10 0 p a c m m p m - 0 0 2 i n p u t c u r r e n t ( a ) buck mode hibernate input current vs. input voltage input voltage (v) 90 135 180 225 270 0.30 0.25 0.20 0.15 0.10 0.05 0 p a c m m p m - 0 0 4 i n p u t p o w e r ( w ) ac/dc flyback mode standby power vs. input voltage input voltage (v ac ) v p = 12v, all regulators on r startup = 1m r startup = 2m
PAC5253 power application controller 11. configurable analog front end (cafe) 11.1. block diagram - 28 - rev 1.10? january 28, 2016 figure 11-1 . configurable analog front end ampx configurable analog front end m u x daxp/pcmpx daxn cmpx m u x m u x s/h m u x protect lp dac hp dac offset cal aiox m u x i/o control adc mux a d c p r e - m u x dinx dinx c o n f i g u r a b l e d i g i t a l s i g n a l m a t r i x c o n f i g u r a b l e a n a l o g s i g n a l m a t r i x phcx m u x m u x dinx phase ref int2/pos phase pos pr1, pr2 phase comparator comparator afe i/o pga diff-pga & pcomp pbtn buf6 push button m u x v sys int1 v temp , v mon , v ref /2 v sys (except aio6) 3v v thref
PAC5253 power application controller 11.2. functional description the device includes a configurable analog front end (cafe, figure 11-1 ) accessible through up to 10 analog and i/o pins. these pins can be configured to form flexible interconnected circuitry made up of up to 3 differential programmable gain amplifiers, 4 single-ended programmable gain amplifiers, 4 general purpose comparators, 3 phase comparators, 10 protection comparators, and one buffer output. these pins can also be programmed as analog feed-through pins, or as analog front end i/o pins that can function as digital inputs or digital open-drain outputs. the pac proprietary configurable analog signal matrix (casm) and configurable digital signal matrix (cdsm) allow real time asynchronous analog and digital signals to be routed in flexible circuit connections for different applications. a push button function is provided for optional push button on, hibernate, and off power management function. 11.2.1. differential programmable gain amplifier (da) the daxp and daxn pin pair are positive and negative inputs, respectively, to a differential programmable gain amplifier. the differential gain can be programmable to be 1x, 2x, 4x, 8x, 16x, 32x, and 48x for zero ohm signal source impedance. the differential programmable gain amplifier has -0.3v to 3.5v input common mode range, and its output can be configured for routing directly to the adc pre-multiplexer, or through a sample-and-hold circuit synchronized with the adc auto-sampling mechanism. each differential amplifier is accompanied by offset calibration circuitry, and two protection comparators for protection event monitoring. the programmable gain differential amplifier is optimized for use with signal source impedance lower than 500 and with matched source impedance on both positive and negative inputs for minimal offset. the effective gain is scaled by 1 3.5k / (13.5k + r source ), where r source is the matched source impedance of each input . 11.2.2. single-ended programmable gain amplifier (amp) each ampx input goes to a single-ended programmable gain amplifier with signal relative to v ssa . the amplifier gain can be programmed to be 1x, 2x, 4x, 8x, 16x, 32x, and 48x, or as analog feed-through. the programmable gain amplifier output is routed via a multiplexer to the configurable analog signal matrix casm. 11.2.3. general purpose comparator (cmp) the general purpose comparator takes the cmpx input and compares it to either the programmable threshold voltage (v thref ) or a signal from the configurable analog signal matrix casm. the comparator has 0v to v sys input common mode range, and its polarity-selectable output is routed via a multiplexer to either a data input bit or the configurable digital signal matrix cdsm. each general purpose comparator has two mask bits to prevent or allow rising or falling edge of its output to trigger second microcontroller interrupt int2, where int2 can be configured to activate protection event pr1. each comparator output, routed via casm and with 500ns de-glitch time, can also be configured to activate protection event pr1. 11.2.4. phase comparator (phc) the phase comparator takes the phcx input and compares it to either the programmable threshold voltage (v thref ) or a signal from the configurable analog signal matrix casm. the comparison signal can be set to a phase reference signal generated by averaging the phcx input voltages. in a three-phase motor control application, the phase reference signal acts as a virtual center tap for bemf detection. the phcx inputs are optionally fed through to the casm. the phase comparator has 0v to v sys input common mode range, and its polarity-selectable output is routed to a data input bit and to the phase/position multiplexer synchronized with the auto-sampling sequencers. 11.2.5. protection comparator (pcmp) two protection comparators are provided in association with each differential programmable gain amplifier, with outputs available to trigger protection events and accessible as read-back output bits. the high-speed protection (hp) comparator compares the pcmpx pin to the 8-bit hp dac output voltage, with full scale voltage of 2.5v. the limit protection (lp) comparator compares the differential programmable gain amplifier output to the 10-bit lp dac output voltage, with full scale voltage of 2.5v. each protection comparator has a mask bit to prevent or allow it to trigger the main microcontroller interrupt int1. each protection comparator also has one mask bit to prevent or allow it to activate protection event pr1, and another mask bit to - 29 - rev 1.10? january 28, 2016
PAC5253 power application controller prevent or allow it to activate protection event pr2. these two protection events can be used directly by protection circuitry in the application specific power drivers (aspd) to protect devices being driven. 11.2.6. analog output buffer (buf) a subset of the signals from the configurable analog signal matrix casm can be multiplexed to the buf6 pin for external use. the buffer offset voltage can be minimized with the built-in swap function. 11.2.7. analog front end i/o (aio) up to 10 aiox pins are available in the device. in the analog front end i/o mode, the pin can be configured to be a digital input or digital open-drain output. the aiox input or output signal can be set to a data input or output register bit, or multiplexed to one of the signals in the configurable digital signal matrix cdsm. the signal can be set to active high (default) or active low, with v sys supply rail. where aio 6,7,8,9 supports microcontroller interrupt for external signals. each has two mask bits to prevent or allow rising or falling edge of its corresponding digital input to trigger second microcontroller interrupt int2. 11.2.8. push button (pbtn) the push button pbtn, when enabled, can be used by the microcontroller to detect a user active-low push button event and to put the system into an ultra-low-power hibernate mode. once the system is in hibernate mode, pbtn can be used to wake up the system. in addition, pbtn can also be used as a hardware reset for the microcontroller when it is held low for longer than 8s during normal operation. the pbtn input is active low and has a 55k pull-up resistor to 3v. 11.2.9. hp dac and lp dac the 8-bit hp dac can be used as the comparison voltage for the high-speed protection (hp) comparators, or routed for general purpose use via the ab2 signal in the casm. the hp dac output full scale voltage is 2.5v. the 10-bit lp dac can be used as the comparison voltage for the limit protection (lp) comparators, or routed for general purpose use via the ab3 signal in the casm. the lp dac output full scale voltage is 2.5v. 11.2.10. adc pre-multiplexer the adc pre-multiplexer is a 16-to-1 multiplexer that selects between the 3 differential programmable gain amplifier outputs, ab1 through ab9, temperature monitor signal (v temp ), power monitor signal (v mon ), and offset calibration reference (v ref / 2). the adc pre-multiplexer can be directly controlled or automatically scanned by the auto-sampling sequencer. when the adc pre-multiplexer is automatically scanned, the unbuffered or sensitive signals should be masked by setting appropriate register bits. 11.2.11. configurable analog signal matrix (casm) the casm has 9 general purpose analog signals labeled ab1 through ab9 that can be used for: routing the single-ended programmable gain amplifier or analog feed-through output to ab1 through ab9 routing an analog signal via ab1, ab2, or ab3 to the negative input of a general purpose comparator or phase comparator routing the 8-bit hp dac output to ab2 routing the 10-bit lp dac output to ab3 routing analog signals via ab1 through ab12 to the adc pre-multiplexer routing phase comparator feed-through signals to ab7, ab8, and ab9, and averaged voltage to ab1 11.2.12. configurable digital signal matrix (cdsm) the cdsm has 7 general purpose bi-directional digital signals labeled db1 through db7 that can be used for: routing the aiox input to or output signals from db1 through db7 routing the general purpose comparator output signals to db1 through db7 - 30 - rev 1.10? january 28, 2016
PAC5253 power application controller - 31 - rev 1.10? january 28, 2016
PAC5253 power application controller 11.3. electrical characteristics table 11 . differential programmable gain amplifier (da) electrical characteristics (v sys = v ccio = 5v, v cc33 = 3.3v, and t a = -40 c to 105 c unless otherwise specified.) parameter conditions min typ max uni t i cc;da operating supply current each enabled amplifier 150 300 a v icmr;da input common mode range -0.3 3.5 v v olr;da output linear range 0.1 3.5 v v os;da input offset voltage gain = 48x, v daxp= v daxn = 0v, t a = 25c -8 8 mv a vzi;da differential amplifier gain (zero ohm source impedance) gain = 1x 1 gain = 2x 2 gain = 4x 4 gain = 8x, v daxp = 125mv, v daxn = 0v, t a = 25c -2% 8 2% gain = 16x 16 gain = 32x 32 gain = 48x 48 k cmrr;da common mode rejection ratio gain = 8x, v daxp= v daxn = 0v, t a = 25c 55 db r indif;da differential input impedance 27 k ? slew rate (1) gain = 8x 7 10 v/s t st;da settling time (1) to 1% of final value 200 400 ns (1) guaranteed by design. table 12 . single-ended programmable gain amplifier (amp) electrical characteristics (v sys = v ccio = 5v, v cc33 = 3.3v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t i cc;amp operating supply current each enabled amplifier 80 140 a v olr;amp output linear range 0.1 3.5 v v os;amp input offset voltage gain = 1x, t a = 25c, v ampx = 2.5v -10 10 mv a v;amp amplifier gain gain = 1x 1 gain = 2x 2 gain = 4x 4 gain = 8x, v ampx = 125mv, t a = 25c -2% 8 2% gain = 16x 16 gain = 32x 32 gain = 48x 48 i in;amp input current 0 1 a slew rate (1) gain = 8x 8 12 v/s t st;amp settling time (1) to 1% of final value 150 300 ns (1) guaranteed by design. - 32 - rev 1.10? january 28, 2016
PAC5253 power application controller table 13 . general purpose comparator (cmp) electrical characteristics (v sys = v ccio = 5v, v cc33 = 3.3v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t i cc;cmp operating supply current each enabled comparator 35 110 a v icmr;cmp input common mode range 0 v sys v v os;cmp input offset voltage v cmpx = 2.5v, t a = 25c -10 10 mv v hys;cmp hysteresis 23 mv i in;cmp input current 0 1 a t del;cmp comparator delay (1) 0.1 s (1) guaranteed by design. table 14 . phase comparator (phc) electrical characteristics (v sys = v ccio = 5v, v cc33 = 3.3v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t i cc;phc operating supply current each enabled comparator 35 110 a v icmr;phc input common mode range 0 v sys v v os;phc input offset voltage v phcx = 2.5v, t a = 25c -10 10 mv v hys;phc hysteresis 23 mv i in;phc input current 0 1 a t del;phc comparator delay (1) 0.1 s (1) guaranteed by design. table 15 . protection comparator (pcmp) electrical characteristics (v sys = v ccio = 5v, v cc33 = 3.3v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t i cc;pcmp operating supply current each enabled comparator 35 100 a v icmr;pcmp input common mode range 0.3 v sys -1 v v os;pcmp input offset voltage v pcmpx = 2.5v, t a = 25c -10 10 mv v hys;pcmp hysteresis 20 mv i in;pcmp input current 0 1 a t del;pcmp comparator delay (1) 0.1 s (1) guaranteed by design. table 16 . analog output buffer (buf) electrical characteristics (v sys = v ccio = 5v, v cc33 = 3.3v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t i cc;buf operating supply current no load 35 100 a v icmr;buf input common mode range 0.05 3.5 v v olr;amp output linear range 0.1 3.5 v v os;buf offset voltage v buf = 2.5v, t a = 25c -18 18 mv i omax maximum output current c l = 0.1nf 0.8 1.3 ma - 33 - rev 1.10? january 28, 2016
PAC5253 power application controller - 34 - rev 1.10? january 28, 2016
PAC5253 power application controller table 17 . analog front end i/o (aio) electrical characteristics (v sys = v ccio = 5v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t v aio pin voltage range 0 5 v v ih;aio high-level input voltage 2.2 v v il;aio low-level input voltage 0.8 v r pd;aio pull-down resistance input mode 0.5 1 1.8 m ? v ol;aio low-level output voltage i aiox = 7ma, open-drain output mode 0.4 v i ol;aio low-level output sink current v aiox = 0.4v, open-drain output mode 6 14 ma i lk;aio high-level output leakage current v aiox = 5v, open-drain output mode 0 10 a table 18 . push button (pbtn) electrical characteristics (v sys = v ccio = 5v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t v i;pbtn input voltage range 0 5 v v ih;pbtn high-level input voltage 2 v v il;pbtn low-level input voltage 0.35 v r pu;pbtn pull-up resistance to 3v, push button input mode 40 55 95 k? table 19 . hp dac and lp dac electrical characteristics (v sys = v ccio = 5v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t v dacref dac reference voltage t a = 25c 2.480 2.5 2.520 v t a = - 40c to 105c 2.453 2.5 2.547 hp 8-bit dac inl (1) -1 1 lsb hp 8-bit dac dnl (1) -0.5 0.5 lsb lp 10-bit dac inl (1) -2 2 lsb lp 10-bit dac dnl (1) -1 1 lsb (1) guaranteed by design and characterization. - 35 - rev 1.10? january 28, 2016
PAC5253 power application controller 11.4. typical performance characteristics (v sys = 5v and t a = 2 5 c unless otherwise specified.) - 36 - rev 1.10? january 28, 2016 0 500 1000 1500 2000 2500 5000 4000 3000 2000 1000 0 p a c c a f e - 0 0 1 o u t p u t v o l t a g e ( m v ) differential pga (dax) gain characteristics at 1x, 2x, 4x, and 8x settings differential input voltage (mv) 1x 2x 4x 8x 0 50 100 150 200 250 p a c c a f e - 0 0 2 o u t p u t v o l t a g e ( m v ) differential pga (dax) gain characteristics at 16x, 32x, and 48x settings differential input voltage (mv) 16x 5000 4000 3000 2000 1000 0 32x 48x 0 100h 200h 300h 3ffh 2500 2000 1500 1000 500 0 p a c c a f e - 0 0 5 o u t p u t v o l t a g e ( m v ) lp dac output voltage vs. input code input code 0 500 1000 1500 2000 2500 p a c c a f e - 0 0 3 o u t p u t v o l t a g e ( m v ) pga (ampx) gain characteristics at 1x, 2x, 4x, and 8x settings input voltage (mv) 5000 4000 3000 2000 1000 0 1x 2x 4x 8x 0 40h 80h c0h ffh 2500 2000 1500 1000 500 0 p a c c a f e - 0 0 6 o u t p u t v o l t a g e ( m v ) hp dac output voltage vs. input code input code p a c c a f e - 0 0 4 o u t p u t v o l t a g e ( m v ) pga (ampx) gain characteristics at 16x, 32x, and 48x settings input voltage (mv) 0 50 100 150 200 250 16x 32x 48x 5000 4000 3000 2000 1000 0
PAC5253 power application controller 12. application specific power drivers (aspd) 12.1. features 4 low-side and 3 ultra-high-voltage high-side gate drivers configurable delays and fast fault protection 12.2. block diagram 12.3. functional description the application specific power drivers (aspd, figure 12-1 ) module handles power driving for power control applications. PAC5253 has four low-side gate drivers (drlx), three ultra-high-voltage high-side gate drivers (dxhx). each gate driver can drive an external mosfet or igbt switch in response to high-speed control signals from the microcontroller ports, and a pair of high-side and low-side gate drivers can form a half-bridge driver. the open-drain drivers provide activation control for relays, leds, buffers, and other loads. figure 12-2 below shows typical gate driver connections and table 20 shows the aspd resources available on PAC5253. - 37 - rev 1.10? january 28, 2016 figure 12-1 . application specific power drivers dxhx dxbx dxsx level shift delay hs1 drlx low-side gate drivers delay high-side gate drivers v p application specific power drivers endrv fault protect ls1 ls2 p o r t / p w m s i g n a l s pre- driver pre- driver
PAC5253 power application controller table 20 . power driver resources by part number part number low-side gate driver high-side gate driver open-drain driver drlx source / sink current dxhx max supply source/ sink current omx PAC5253 4 1a/1a 3 600v 0.25a/0.5a 2 (23v/ 40ma) the aspd includes built-in configurable fault protection for the internal gate drivers. 12.3.1. low-side gate driver the drlx low-side gate driver drives the gate of an external mosfet or igbt switch between the low-level v ssp power ground rail and high-level v p supply rail. the drlx output pin has sink and source output current capability of 1a. each low-side gate driver is controlled by a microcontroller port signal with 4 configurable levels of propagation delay. 12.3.2. ultra-high-voltage gate driver the dxhx ultra-high-voltage high-side gate driver drives the gate of an external mosfet or igbt switch between its low-level dxsx driver source rail and its high-level dxbx bootstrap rail. the dxsx pin can go up to 600v. the dxhx output pin has 0.5a sink and 0.25a source output current capability. the dxbx bootstrap pin can have a maximum operating voltage of 20v relative to the dxsx pin. the dxsx pin is designed to tolerate momentary switching negative spikes down to -10v without affecting the dxhx output state. each ultra-high-voltage high-side gate driver is controlled by a microcontroller port signal. for bootstrapped high-side operation, connect a n appropriate capacitor between dxbx and dxsx and a properly rated bootstrap diode from v p rail to dxbx. 12.3.3. high-side switching transients typical high-side switching transients are shown in figure 12-3 (a). to ensure functionality and reliability, the dxsx and dxbx pins must not exceed the peak and undershoot limit values shown. this should be verified by probing the dxsx and dxbx pins directly relative to vss pin. a small resistor and diode clamp for the dxsx pin can be used to make sure that the pin voltage stays within the negative limit value. in addition, the high-side slew rate dv/dt must be kept within 50v/ns for dxsx. this can be achieved by adding a resistor-diode pair in series, and an optional capacitor in parallel with the power switch gate. the parallel capacitor also provides a low impedance and close gate shunt against coupling from the switch drain. these optional protection and slew rate control are shown in figure 12-3 (b). - 38 - rev 1.10? january 28, 2016 figure 12-2 . typical gate driver connections dxhx drlx dxsx dxbx v p v in PAC5253 ( to loads/inductors .)
PAC5253 power application controller 12.3.4. power drivers control all power drivers are initially disabled from power-on-reset. to enable the power drivers, the microprocessor must first set the driver enable bit to '1'. the gate drivers controlled by the microcontroller ports and pwm signals according to table 21 , with configurable delays as shown in table 21 . refer to the pac application notes and user guide for additional information on power drivers control programming. table 21 . microcontroller port and pwm to power driver mapping part number pwma0 pwma1 pwma2 pwma3/ pwma4/ pwmb0 pwma4/ pwmb0 pwma5/ pwma7/ pwmc1 pwma6/ pwmd0 PAC5253 drl0 drl1 drl2 drl3 dxh0 dxh1 dxh2 table 22 . power driver d elay configuration delay setting drlx dxhx rising falling rising falling default setting 130ns 140ns 200ns 240ns 01b setting 170ns 180ns 10b setting 230ns 250ns 11b setting 360ns 380ns 12.3.5. gate driver fault protection the aspd incorporates a configurable fault protection mechanism using two protection event signals from the configurable analog front end (cafe), designated as protection event 1 (pr1) and protection event 2 (pr2) signals. t he drl0/drl1/drl2 drivers are designated as low-side group 1, and t he drl3 gate driver are designed as low-side group 2. the dxh0/dxh1/dxh2 ultra-high-voltage gate drivers are designated as high-side group 1. the pr1 signal from the cafe can be used to disable low-side group 1, high-side group 1, or both depending on the pr1 mask bit settings. the pr2 signal from the cafe can be used to disable low-side group 2, high-side group 2, or both depending on the pr2 mask bit - 39 - rev 1.10? january 28, 2016 figure 12-3 . high-side switching transients and optional circuitry v dxsx v dxsx -10v v dxbx 625 v v dxbx dv/dt dv/dt (a) high-side switching transients (b) optional transient protection and slew rate control dxhx drlx dxsx dxbx v p v in PAC5253
PAC5253 power application controller settings. - 40 - rev 1.10? january 28, 2016
PAC5253 power application controller 12.4. electrical characteristics table 23 . gate drivers electrical characteristics (v p = 12v, v sys = 5v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t low-side gate drivers (drlx pins) v oh,drl high-level output voltage i drlx = -50ma v p ?0.5 v p ?0.25 v v ol,drl low-level output voltage i drlx = 50ma 0.175 0.35 v i ohpk,drl high-level pulsed peak source current 10s pulse -1 a i olpk,drl low-level pulsed peak sink current 10s pulse 1 a t pd,drl propagation delay delay setting 00 10 ns delay setting 01 50 delay setting 10 120 delay setting 11 250 ultra-high-voltage gate drivers (dxhx, dxbx and dxsx pins) v dxs level-shift driver source voltage range repetitive, 10us pulse -10 605 v steady state 0 600 v dxb bootstrap pin voltage range repetitive, 10us pulse 1 625 v steady state 9 620 v bs;dxb bootstrap supply voltage range v dxbx , relative to respective v dxsx 9 20 v v uvlo;dxb bootstrap uvlo threshold v dxbx rising, relative to respective v dxsx , hys=0.5v 6.3 7.5 9.3 v i bs;dxb bootstrap supply current 40 80 a i os;dxb offset supply current v dxbx = v dxsx =600v 10 a v oh;dxh high-level output voltage i dxhx = -20ma v dxbx ?0.6 v v ol;dxh low-level output voltage i dxhx = 40ma v dxsx +0.6 v i ohpk;dxh high-level pulsed peak source current 10s pulse -0.25 a i olpk;dxh low-level pulsed peak sink current 10s pulse 0.5 a table 24 . open-drain drivers electrical characteristics (v p = 12v, v sys = 5v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t medium-voltage open-drain drivers (omx pins) v om output voltage range off state 0 23 v r on;om on state resistance i omx = 20ma 17 35 ? i ol;om on state sink current v omx = 2v 40 80 ma i lk;om leakage current v omx = 23v, off state 0 10 a - 41 - rev 1.10? january 28, 2016
PAC5253 power application controller 12.5. typical performance characteristics (v p = 12v, v sys = 5v and t a = 2 5 c unless otherwise specified.) - 42 - rev 1.10? january 28, 2016 -40 0 40 80 120 25 20 15 10 5 0 p a c a s p d - 0 0 6 o n r e s i s t a n c e ( ) ultra-high-voltage high-side gate driver (dxhx) on resistance vs. temperature temperature ( c) pull down pull up pac5250 -40 0 40 80 120 500 400 300 200 100 0 p a c a s p d - 0 0 7 t u r n - o n d e l a y ( n s ) low-side gate driver (drlx) turn-on delay vs. temperature temperature ( c) 00b setting (default) 11b setting 10b setting c l = 1nf 01b setting -40 0 40 80 120 500 400 300 200 100 0 p a c a s p d - 0 0 8 t u r n - o f f d e l a y ( n s ) low-side gate driver (drlx) turn-off delay vs. temperature temperature ( c) 00b setting (default) 11b setting 10b setting 01b setting c l = 1nf -40 0 40 80 120 1.0 0.8 0.6 0.4 0.2 0 p a c a s p d - 0 0 5 s o u r c e / s i n k c u r r e n t ( a ) ultra-high-voltage high-side gate driver (dxhx) source/sink current vs. temperature temperature ( c) source current sink current pac5250 -40 0 40 80 120 3 2 1 0 p a c a s p d - 0 0 1 s o u r c e / s i n k c u r r e n t ( a ) low-side gate driver (drlx) source/sink current vs. temperature temperature ( c) sink current source current -40 0 40 80 120 8 7 6 5 4 3 2 1 0 p a c a s p d - 0 0 2 o n r e s i s t a n c e ( ) low-side gate driver (drlx) on resistance vs. temperature temperature ( c) pull up pull down
PAC5253 power application controller typical performance characteristics (continued) (v p = 12v, v sys = 5v and t a = 2 5 c unless otherwise specified.) - 43 - rev 1.10? january 28, 2016 -40 0 40 80 120 500 400 300 200 100 0 p a c a s p d - 0 1 1 t u r n - o n d e l a y ( n s ) ultra-high-voltage high-side gate driver (dxhx) turn-on delay vs. temperature temperature ( c) c l = 1nf -40 0 40 80 120 500 400 300 200 100 0 p a c a s p d - 0 1 2 t u r n - o f f d e l a y ( n s ) ultra-high-voltage high-side gate driver (dxhx) turn-off delay vs. temperature temperature ( c) c l = 1nf 0 40 80 120 160 200 4 3 2 1 0 p a c a s p d - 0 1 4 o n s t a t e o u t p u t v o l t a g e ( v ) omx open-drain driver on state output voltage vs. output current output current (ma) 105 c 25 c -30 c
PAC5253 power application controller 13. adc with auto-sampling sequencer 13.1. block diagram 13.2. functional description 13.2.1. adc the analog-to-digital converter (adc) is a 10-bit succesive approximation register (sar) adc with 1 s conversion time an d up to 1msps capability. the adc input clock has a user-configurable divider from /1 to /8 of the system clock. the integrated analog multiplexer allows selection from up to 6 direct adx inputs, and from up to 10 analog inputs signals in the configurable analog front end (cafe), including up to 3 differential input pairs. the adc can be configured for repeating or non-repeating conversions and can interrupt the microcontroller when a conversion is finished. 13.2.2. auto-sampling sequencer two independent and flexible auto-sampling sequencer state machines allow signal sampling using the adc without interaction from microcontroller core. each auto-sampling sequencer state machine can be programmed to take and store up to 8 samples each in the adc result register from different analog inputs, able to control the adc mux and adc premux as well as the precise timing of the s/h in the configurable analog front end. the sampling start of the auto-sampling sequencer can be precisely triggered using timers a, b, c, or d or any of their associated pwm edges (high-to-low or low- to-high). it also supports manual start or a ping-pong-scheme, where one auto-sampling sequencer state machine triggers the other when it finishes sampling. the auto - sampling sequencer can interrupt the microcontroller when either conversion sequence is finished. - 44 - rev 1.10? january 28, 2016 figure 13-1 . adc with auto-sampling sequencer adc a h b / a p b adc with auto-sampling sequencer adx m u x a d c p r e - m u x v temp , v mon , v ref /2 register emux s/h 10-bit adc daxp daxn differential pga diff-pga m u x configurable analog front end c a s m auto-sampling sequencer adc result registers (16) emux control state machine 1 state machine 0 register register register
PAC5253 power application controller 13.2.3. emux control a dedicated low latency interface controllable by the auto-sampling sequencer or register control allows changing the adc premultiplexer and asserting/deasserting the s/h circuit in the configurable analog front end, allowing back to back conversions of multiple analog inputs without microcontroller interaction. 13.3. electrical characteristics table 25 . adc and auto-sampling sequencer electrical characteristics (v sys = v ccio = 5v, v cc33 = 3.3v, v cc18 = 1.8v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t adc f adclk adc conversion clock input 16 mhz t adconv adc conversion time f adclk = 16mhz 1 s adc resolution 10 bits adc effective resolution 9.2 bits adc differential non-linearity (dnl) 0.5 lsb adc integral non-linearity (inl) 1 lsb adc offset error 0.6 %fs adc gain error 0.12 %fs reference voltage v refadc adc reference voltage input 2.5 v sample and hold t adcsh adc sample and hold time f adclk = 16mhz 188 ns c adcic adc input capacitance 1.3 pf input voltage range v adcin adc input voltage range adc multiplexer input 0 v refadc v emux clock speed f emuxclk emux engine clock input 50 mhz pll clock speed f outpll pll output frequency t a = -40 c to 85 c 3.5 100 mhz t a = 85 c to 105 c 3.5 80 mhz - 45 - rev 1.10? january 28, 2016
PAC5253 power application controller 14. memory system 14.1. features 32kb embedded flash 100,000 program/erase cycles 10 years data retention 8kb sram 14.2. block diagram 14.3. functional description the device has multiple banks of embedded flash memory, sram memory, as well as peripheral control registers that are all program-accessible in a flat memory map. 14.3.1. program and data flash 32kb in 32 pages of 1kb each is available for program or data memory. each of them can be individually erased or written to while the microcontroller is executing a program from sram. 14.3.2. sram up to 8kb contiguous array of sram is available for non-persistent data storage. the sram memory supports word (4 - byte), half-word (2-byte) and byte address aligned access. the microcontroller may execute code out of sram for time- critical applications, or when modifying the contents of flash memory. - 46 - rev 1.10? january 28, 2016 figure 14-1 . memory system 8kb sram a h b / a p b memory system 1kb flash pages flash 256b info rom info rom sram
PAC5253 power application controller 14.4. electrical characteristics table 26 . memory system electrical characteristics (v sys = v ccio = 5v, v cc33 = 3.3v, v cc18 = 1.8v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t embedded flash t read;flash flash read time 40 ns t write;flash flash write time 20 s t perase;flash flash page erase time 10 ms n perase;flash flash program/erase cycles 100k cycles t dr;flash flash data retention 10 years sram t sram sram access cycle time 20 ns - 47 - rev 1.10? january 28, 2016
PAC5253 power application controller 15. clock control system 15.1. features ring oscillator with 7.5mhz, 9.6mhz, 13.8mhz, and 25.7mhz settings high accuracy 1% trimmed 4mhz rc oscillator crystal oscillator driver supporting 2mhz to 10mhz crystals external clock input up to 40mhz pll with 1mhz to 25 mhz input, and 3.5mhz to 100mhz output /1 to /8 clock divider for hclk /1 to /128 clock divider for aclk 15.2. block diagram - 48 - rev 1.10? january 28, 2016 xin xout extclk m u x crystal driver 1% rc oscillator ring oscillator pll m u x div div hclk clock sources pll clock tree div rtc div wdt div wic div adc div cortex m0 systick sram flash div uart div i2c div soc bus div spi div adc emux clock gating timers a, b, c & d clock gating clock gating aclk fclk frclk clock control system timer div figure 15-1 . clock control system xin xout extclk m u x crystal driver 1% rc oscillator ring oscillator pll m u x div div hclk clock sources pll clock tree div rtc div wdt div wic div adc div cortex m0 systick sram flash div uart div i2c div soc bus div spi div adc emux clock gating timers a, b, c & d clock gating clock gating aclk fclk frclk clock control system timer div f r c l k
PAC5253 power application controller 15.3. functional description the pac clock control system covers a wide range of applications. 15.3.1. free running clock (frclk) the free running clock (frclk) is generated from one of the 4 clock sources: ring oscillator, trimmed rc oscillator, crystal driver or external clock input. the frclk is used for the real-time clock (rtc), watchdog timer (wdt), input to the pll, or fclk source to clock the system in low power and sleep mode. 15.3.2. fast clock (fclk) the fast clock (fclk) is generated from the pll or supplied by the frclk directly. the fclk supplies the watchdog timer (wdt), adc, wake-up interrupt controller (wic), systick timer, arm cortex-m0 peripheral high speed clock (hclk) and low speed clock (lsclk). 15.3.3. high-speed clock (hclk) the high-speed clock (hclk) is derived from the fclk with a /1, /2, /4 or /8 divider. it supplies the peripheral ahb/apb bus, timers a to d, dead-time controllers, spi interface, i 2 c interface, uart interface, emux interface, soc bridge interface and memory subsystem, and can go as high as 50mhz. 15.3.4. auxiliary clock (aclk) the auxiliary clock (aclk) is derived from fclk with a /1, /2, to /128 divider, and supplies the timer and dead - time blocks. it can be clocked faster or slower than hclk and can go as high as 100mhz. 15.3.5. clock gating the clock tree supports clock gating in deep-sleep mode for the timer block, adc, spi interface, i 2 c interface, uart interface, memory subsystem and the arm cortex-m0 itself. 15.3.6. ring oscillator (rosc) the integrated ring oscillator provides 4 different clocks with 7.5mhz, 9.6mhz, 13.8mhz, and 25.7mhz settings. after reset, the clock tree always defaults to this clock input with the lowest frequency setting. 15.3.7. trimmed 4mhz rc oscillator the 1% trimmed 4mhz rc oscillator provides an accurate clock suitable for many applications. it is also used to derive the clock for the multi-mode power manager. 15.3.8. internal slow rc oscillator an internal 32khz rc oscillator is used during start up to provide an initial clock to analog circuitry. it is not used as a clock input to the clock tree. 15.3.9. crystal oscillator driver the optional crystal oscillator driver can drive crystals from 2mhz to 10mhz to provide a highly accurate and stable clock into the system. 15.3.10. external clock input the clock tree can be supplied with an external clock up to 10mhz. 15.3.11. pll the integrated pll input clock is supplied by the frclk with an input frequency range of 1mhz to 25mhz. the pll output frequency is adjustable from 3.5mhz to 100mhz. - 49 - rev 1.10? january 28, 2016
PAC5253 power application controller 15.4. electrical characteristics table 27 . clock control system electrical characteristics (v sys = v ccio = 5v, v cc33 = 3.3v, v cc18 = 1.8v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t clock tree (frclk, fclk, hclk, and aclk) f frclk free running clock frequency 50 mhz f fclk fast clock frequency 100 mhz f hclk high-speed clock frequency 50 mhz f aclk auxiliary clock frequency 100 mhz internal oscillators f rosc ring oscillator frequency frequency setting = 11b 7.5 mhz frequency setting = 10b 9.6 frequency setting = 01b 13.8 frequency setting = 00b 25.7 f trim trimmed rc oscillator frequency t a = 25 c 3.96 4 4.04 mhz t a = -40 c to 105 c 3.90 4 4.06 trimmed rc oscillator clock jitter t a = -40 c to 85 c 0.5 % crystal oscillator driver v ih;xin xin h igh-level input voltage 0.65 ? v cc18 v v il;xin xin l ow-level input voltage 0.35 ? v cc18 v f xtal crystal oscillator frequency range 2 10 mhz recommended capacitive load f xtal = 2mhz to 3mhz 25 pf f xtal = 3mhz to 6mhz 20 f xtal = 6mhz to 10mhz 16 external circuit esr f xtal = 2mhz to 3mhz 1000 f xtal = 3mhz to 6mhz 400 f xtal = 6mhz to 10mhz 100 external clock input f extclk external clock input frequency range 40 mhz t high;extclk external clock high time 10 ns t low;extclk external clock low time 10 ns pll f inpll pll input frequency range 2 25 mhz f outpll pll output frequency range 3.5 100 mhz pll settling time 0.5 ms pll period jitter rms 30 ps peak to peak 150 - 50 - rev 1.10? january 28, 2016
PAC5253 power application controller 16. arm cortex-m0 microcontroller core 16.1. features arm cortex-m0 core fast single-cycle 32-bit x 32-bit multiplier 24-bit systick timer up to 50mhz operation serial wire debug (swd), with 4 break-point and 2 watch-point unit comparators nested vectored interrupt controller (nvic) with 25 external interrupts wake-up interrupt controller (wic) with gpio, real-time clock (rtc) and watchdog timer (wdt) interrupts enabled sleep and deep-sleep mode with clock gating 16.2. block diagram 16.3. functional description the arm cortex-m0 microcontroller core is configured for little endian operation and includes the fast single - cycle 32-bit multiplier and 24-bit systick timer and can operate at a frequency of up to 50mhz. the microcontroller nested vectored interrupt controller (nvic) supports 25 external interrupts for the device's peripherals and sub-systems. for low-latency interrupt processing, the nvic also supports interrupt tail-chaining. the wake-up interrupt controller (wic) is able to wake up the device from low-power modes using any gpio interrupt, as well as from the rtc or wdt. the arm cortex-m0 supports both sleep and deep-sleep low-power modes. the deep-sleep mode supports clock gating to limit standby power even further. firmware debug support includes 4 break-point and 2 watch-point unit comparators using the serial wire debug (swd) protocol. the serial wire debug mechanism can be disabled to prevent device access to the firmware in the field. - 51 - rev 1.10? january 28, 2016 figure 16-1 . arm cortex-m0 microcontroller core serial wire debug with disable arm cortex-m0 a h b / a p b arm cortex-m0 microcontroller core 1-cycle 32x32 multiplier wake-up interrupt controller 24-bit systick swdda swdcl nested vectored interrupt controller
PAC5253 power application controller 16.4. electrical characteristics table 28 . microcontroller and clock control system electrical characteristics (v sys = v ccio = 5v, v cc33 = 3.3v, v cc18 = 1.8v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t f hclk microcontroller clock hclk 50 mhz i op;vsys v sys operating supply current f frclk = f hclk = f aclk = rosc 11b, pll disabled, cpu halt; other clock sources, adc, timers, and serial interface disabled 3.4 ma f frclk = f hclk = f aclk = rosc 10, pll disabled, cpu halt; other clock sources, adc, timers, and serial interface disabled 4 f frclk = f hclk = f aclk = rosc 01, pll disabled, cpu halt; other clock sources, adc, timers, and serial interface disabled 5.3 f frclk = f hclk = f aclk = rosc 00, pll disabled, cpu halt; other clock sources, adc, timers, and serial interface disabled 9 f frclk = f hclk = f aclk = clkref, pll disabled, cpu halt; other clock sources, adc, timers, and serial interface disabled 2.3 f frclk = f hclk = f aclk = 10mhz xtal, pll disabled, cpu halt; other clock sources, adc, timers, and serial interface disabled 4.5 f frclk = 4mhz clkref, f hclk = 50mhz, f aclk = f outpll = 100mhz, cpu halt; other clock sources, adc, timers, and serial interface disabled 23.3 i q;vccio v ccio quiescent supply current 0.02 ma 16.5. typical performance characteristics ( v sys = v ccio = 5v, v cc33 = 3.3v, v cc18 = 1.8v, and t a = 2 5 c unless otherwise specified.) - 52 - rev 1.10? january 28, 2016 0 20 40 60 80 100 25 20 15 10 5 0 p a c m c u - 0 0 1 i v c c 1 8 ( m a ) i vcc18 vs. pll frequency pll frequency (mhz) f hclk = f aclk = f outpll f hclk = 0.5 ? f outpll , f aclk = f outpll
PAC5253 power application controller 17. i/o controller 17.1. features 5v-compliant i/o pax, pdx, pex 3.3v-compliant i/o pcx configurable drive strength on pax, pdx, pex configurable pull-up or pull-down on pax, pdx, pex 17.2. block diagram 17.3. functional description the pac can support up to 4 ports with 8 i/os each from pax, pcx, pdx, and pex, in addition to the i/os on the analog front end. all pax, pcx, pdx, and pex ports have interrupt capability with configurable interrupt edge. pax, pdx, and pex i/os use v ccio as the i/o supply voltage that is 5v on default parts (and 3.3v available from factory). the drive current can be configured as 8ma or 16ma. they also support weak pull-up and pull-down to save external components. pcx uses v cc33 as its i/o supply voltage. the drive current is fixed to 8ma. pc0 to pc5 are also associated with analog inputs ad0 to ad5 to the adc. - 53 - rev 1.10? january 28, 2016 figure 17-1 . i/o controller pax, pdx, pex digital i/o gpio input v ccio (5v/3.3v) gpio output output enable drive strength pull up pull down v ccio (5v/3.3v) pcx gpio input gpio output output enable v cc33 (3.3v) input enable adc mux a h b / a p b peripheral peripheral gpio (pcx) gpio (pax, pdx, pex)
PAC5253 power application controller 17.4. electrical characteristics table 29 . i/o controller electrical characteristics (v sys = v ccio = 5v, v cc33 = 3.3v, v cc18 = 1.8v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t pax, pdx, pex (5v operation) v ih high-level input voltage v ccio = 5v 3 v v il low-level input voltage v ccio = 5v 0.8 v i ol low-level output sink current v ccio = 5v, v ol = 0.4v drive strength setting = 0b 7 ma drive strength setting = 1b 15 i oh high-level output source current v ccio = 5v, v oh = 2.4v drive strength setting = 0b -7 ma drive strength setting = 1b -15 r pu weak pull-up resistance v ccio = 5v 53 66 87 k r pd weak pull-down resistance v ccio = 5v 63 108 244 k i il input leakage current t a = 125 c -10 0 10 a pax, pdx, pex (3.3v operation) v ih high-level input voltage v ccio = 3.3v 2 v v il low-level input voltage v ccio = 3.3v 0.8 v i ol low-level output sink current v ccio = 3.3v, v ol = 0.4v drive strength setting = 0b 4 ma drive strength setting = 1b 8 i oh high-level output source current v ccio = 3.3v, v oh = 2.4v drive strength setting = 0b -4 ma drive strength setting = 1b -8 r pu weak pull-up resistance v ccio = 3.3v 47 74 104 k r pd weak pull-down resistance v ccio = 3.3v 50 84 121 k i il input leakage current t a = 125 c -10 0 10 a pcx (3.3v operation) v ih high-level input voltage v cc33 = 3.3v 2 v v il low-level input voltage v cc33 = 3.3v 0.8 v i ol low-level output sink current v cc33 = 3.3v, v ol = 0.4v 7 ma i oh high-level output source current v cc33 = 3.3v, v oh = 2.4v -7 ma i il input leakage current t a = 125 c -10 0 10 a - 54 - rev 1.10? january 28, 2016
PAC5253 power application controller 18. serial interface 18.1. block diagram 18.2. functional description the device has up to three serial interfaces: i 2 c, uart, and spi. 18.2.1. i 2 c controller the i 2 c controller is a configurable peripheral that can support various modes of operation: i 2 c master operation normal mode (100khz), fast mode (400khz), or fast mode plus (1mhz) single and multi-master synchronization (multi-master) arbitration (multi-master) 7-bit or 10-bit slave addressing i 2 c slave operation normal mode (100khz), fast mode (400khz), or fast mode plus (1mhz) clock stretching 7-bit or 10-bit slave addressing the i 2 c peripheral may operate either by polling, or can be configured to be interrupt driven for both receive and transmit - 55 - rev 1.10? january 28, 2016 figure 18-1 . serial interface scl serial interface sda i 2 c master i 2 c slave i 2 c a h b / a p b spiclk spimiso spi master spi spimosi spics0, 1, 2 tx rx 16550-compatible uart uart spi slave
PAC5253 power application controller data. 18.3. uart controller the uart peripheral is a configurable peripheral that can support various features and modes of operation: programmable clock selection national instruments pc16550d compatible 16-deep transmit and receive fifo and fractional clock divisor up to 3.125mbps communication speed (with hclk = 50mhz) the uart peripheral may operate either by polling, or can be configured to be interrupt driven for both receive and transmit data. 18.4. spi controller the device contains an spi controller that can each be used in either master or slave operation, with the following features: spi master operation control of up to three different spi slaves operation up to 25mhz flexible multiple transmit mode for variable-size spi data with user-defined chip-select behavior chip select shaping through programmable additional delay for chip-select setup, hold and wait time for back-to-back transfers spi master or slave operation supports clock phase and polarity control data transmission/reception can be on 8-, 16-, 24- or 32-bit boundary selectable data bit ordering (lsb or msb first) programmable chip select polarity selectable auto-retransmit mode the spi peripheral may operate either by polling, or can be configured to be interrupt driven for both receive and transmit data. - 56 - rev 1.10? january 28, 2016
PAC5253 power application controller 18.5. dynamic characteristics table 30 . serial interface dynamic characteristics (v sys = v ccio = 5v, v cc33 = 3.3v, v cc18 = 1.8v, and t a = -40 c to 105 c unless otherwise specified.) symbol parameter conditions min typ max uni t i 2 c f i2cclk i 2 c input clock frequency standard mode (100khz) 2.8 mhz fast mode (400khz) 2.8 mhz fast mode plus (1mhz) 6.14 mhz uart f uartclk uart input clock frequency f hclk /16 mhz uart baud rate f hclk = 50mhz 3.125 mbps spi f spiclk spi input clock frequency master mode f hclk /2 mhz slave mode f hclk /2 mhz - 57 - rev 1.10? january 28, 2016
PAC5253 power application controller table 31 . i 2 c dynamic characteristics symbol parameter conditions min typ max unit f scl scl clock frequency standard mode 0 100 fast mode 0 400 fast mode plus 0 1000 khz t low scl clock low standard mode 4.7 fast mode 1.3 fast mode plus 0.5 s t high scl clock high standard mode 4.0 fast mode 0.6 fast mode plus 0.26 s t hd;sta hold time for a repeated start condition standard mode 4.0 fast mode 0.6 fast mode plus 0.26 s t su;sta set-up time for a repeated start condition standard mode 4.7 fast mode 0.6 fast mode plus 0.26 s t hd;dat data hold time standard mode 0 3.45 fast mode 0 0.9 fast mode plus 0 s t su;dat data set-up time standard mode 250 fast mode 100 fast mode plus 50 ns t su;sto set-up time for stop condition standard mode 4.0 fast mode 0.6 fast mode plus 0.26 s t buf bus free time between a stop and start condition standard mode 4.7 fast mode 1.3 fast mode plus 0.5 s t r rise time for sda and scl standard mode 1000 fast mode 20 300 fast mode plus 120 ns t f fall time for sda and scl standard mode 300 fast mode 300 fast mode plus 120 ns c b capacitive load for each bus line standard mode, fast mode 400 pf fast mode plus 550 pf - 58 - rev 1.10? january 28, 2016
PAC5253 power application controller - 59 - rev 1.10? january 28, 2016 figure 18-2 . i 2 c timing diagram s sr p s sda scl t hd;sta t high t low t su;sta t r t f t buf t su;sto t f t r t su;dat t hd;dat
PAC5253 power application controller 19. timers 19.1. block diagram - 60 - rev 1.10? january 28, 2016 figure 19-1 . timers a, b, c, and d pwma0, pwma1, pwma2, pwma3 timers a, b, c, and d a h b / a p b dead time generator pwma4, pwma5, pwma6, pwma7 capture & compare capture & compare timer a 16-bit pwmb0 dead time generator pwmb1 capture & compare capture & compare pwmc0 dead time generator pwmc1 capture & compare capture & compare pwmd0 dead time generator pwmd1 capture & compare capture & compare timer b 16-bit timer c 16-bit timer d 16-bit timer a pwm timer b pwm timer c pwm timer d pwm s y n c
PAC5253 power application controller 19.2. functional description the device includes 9 timers: timer a, timer b, timer c, timer d, watchdog timer 1 (wdt), watchdog timer 2, wake-up timer, real-time clock (rtc), and systick timer. the device supports up to 14 different pwm signals and has up to 7 dead- time controllers. timers a, b, c and d can be concatenated to synchronize to a single clock and start/stop signal for applications that require a synchronized timer period between timers. 19.2.1. timer a timer a is a general purpose 16-bit timer with 8 pwm/capture and compare units. it has 4 pairs of pwm signals going into 4 dead-time controllers. timer a can be concatenated with timers b, c, and d to synchronize the pwm/capture and compare units. it can use either aclk or hclk as clock input with an additional clock divider from /1 to /128. 19.2.2. timer b timer b is a general purpose 16-bit timer with 2 pwm/capture and compare units. it has one pair of pwm signals going into one dead-time controller, as well as 2 additional compare units that can be used for additional system time bases for interrupts. timer b can be concatenated with timers a, c, and d to synchronize the pwm/capture and compare units. it can use either aclk or hclk as clock input with an additional clock divider from /1 to /128. 19.2.3. timer c timer c is a general purpose 16-bit timer with 2 pwm/capture and compare units. it has one pair of pwm signals going into one dead-time controller. timer c can be concatenated with timers a, b, and d to synchronize the pwm/capture and compare units. it can use either aclk or hclk as clock input with an additional clock divider from /1 to /128. - 61 - rev 1.10? january 28, 2016 figure 19-2 . soc bus watchdog and wake-up timer soc bus watchdog wake-up timer soc soc bus a h b / a p b soc bus watchdog and wake-up timer figure 19-3 . real-time clock and watchdog timer wdt 24-bit rtc 24-bit a h b / a p b real-time clock and watchdog timer
PAC5253 power application controller 19.2.4. timer d timer d is a general purpose 16-bit timer with 2 pwm/capture and compare units. it has one pair of pwm signals going into one dead-time controller. timer d can be concatenated with timers a, b, and c to synchronize the pwm/capture and compare units. it can use either aclk or hclk as clock input with an additional clock divider from /1 to /128. 19.2.5. watchdog timer the 24-bit watchdog timer (wdt) can be used for long time period measurements or periodic wake up from sleep mode. the watchdog timer can be used as a system watchdog, or as an interval timer, or both. the watchdog timer can use either frclk or fclk as clock input with an additional clock divider from /2 to /65536. 19.2.6. soc bus watchdog timer the watchdog timer 2 is used to monitor internal soc bus communication. it will trigger device reset if there is no soc bus communication to the afe for 4s or 8s. 19.2.7. wake-up timer the wake-up timer can be used for very low power hibernate and sleep modes to wake up the micro controller periodically. it can be configured to be 125ms, 250ms, 500ms, 1s, 2s, 4, or 8s. 19.2.8. real-time clock the 24-bit real-time clock (rtc) can be used for time measurements when an accurate clock source is used. this timer can also be used for periodic wake up from sleep mode. the rtc uses frclk as clock input with an additional clock divider from /2 to /65536. - 62 - rev 1.10? january 28, 2016
PAC5253 power application controller 20. thermal characteristics table 32 . thermal characteristics parameter value unit operating ambient temperature range -40 to 105 c operating junction temperature range -40 to 150 c storage temperature range -55 to 150 c lead temperature (soldering, 10 seconds) 300 c junction-to-case thermal resistance ( jc ) tbd c/w junction-to-ambient thermal resistance ( ja ) tbd c/w - 63 - rev 1.10? january 28, 2016
PAC5253 power application controller 21. application examples the following simplified diagrams show different examples of pac applications. refer to application notes for detailed design description. - 64 - rev 1.10? january 28, 2016 figure 21-1 . 3-phase motor using PAC5253 (simplified diagram) vp PAC5253 drm csm v p dxhx drlx dxsx dxbx daxp, daxn interface monitoring signals gpio v ac m figure 21-2 . solar micro-inverter using PAC5253 (simplified diagram) PAC5253 v p dxh0, dxh1 drl0, drl1 dxs0, dxs1 dxb0, dxb1 daxp, daxn drl2 ampx vp drm csm v ac interface monitoring signals gpio
PAC5253 power application controller - 65 - rev 1.10? january 28, 2016 vp pac5250 drm csm v p dxhx drlx dxsx dxbx daxp, daxn interface monitoring signals gpio v ac m figure 21-3 . motor with led lighting using PAC5253 (simplified diagram) vp PAC5253 drm csm v p dxhx drlx dxsx dxbx daxp, daxn drlx ampx interface monitoring signals gpio v ac m
PAC5253 power application controller 22. package outline and dimensions 22.1. tqfn88-43 package outline and dimensions - 66 - rev 1.10? january 28, 2016
PAC5253 power application controller 23. change list version 1.6: ? fixed power manager power up sequence timing diagram - 67 - rev 1.10? january 28, 2016
PAC5253 power application controller 24. legal information copyright ? 2015 active-semi, inc. all rights reserved. all information provided in this document is subject to legal disclaimers. active-semi reserves the right to modify its products, circuitry or product specifications without notice. active-semi products are not intended, designed, warranted or authorized for use as critical components in life-support, life-critical or safety-critical devices, systems, or equipment, nor in applications where failure or malfunction of any active-semi product can reasonably be expected to result in personal injury, death or severe property or environmental damage. active-semi accepts no liability for inclusion and/or use of its products in such equipment or applications. active-semi does not assume any liability arising out of the use of any product, circuit, or any information described in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of active-semi or others. active-semi assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. customers should evaluate each product to make sure that it is suitable for their applications. customers are responsible for the design, testing, and operation of their applications and products using active-semi products. customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. all products are sold subject to active-semi's terms and conditions of sale supplied at the time of order acknowledgment. exportation of any active-semi product may be subject to export control laws. active-semi tm , active-semi logo, solutions for sustainability tm , power application controller tm , micro application controller tm , multi-mode power manager tm , configurable analog front end tm , and application specific power drivers tm are trademarks of active-semi, inc. arm ? is a registered trademark and cortex tm is a trademark of arm limited. all referenced brands and trademarks are the property of their respective owners. for more information on this and other products, contact sales@active-semi.com or visit www.active-semi.com . - 68 - rev 1.10? january 28, 2016

▲Up To Search▲

Price & Availability of PAC5253

	To Download PAC5253 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .